(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of dual damascene metallization using low dielectric constant materials in the manufacture of integrated circuits.
(2) Description of the Prior Art
The damascene or dual damascene process has become a future trend in integrated circuit manufacturing, especially in the copper metallization process. These processes are discussed in ULSI Technology, by Chang and Sze, The McGraw Hill Companies, Inc., NY, N.Y., c. 1996, pp. 444-445. Low dielectric constant materials have been proposed as the dielectric materials in order to reduce capacitance. In the conventional damascene scheme, one or more etch stop and/or barrier layers comprising high dielectric constant materials, such as silicon nitride, are required. This defeats the purpose of the low dielectric constant materials. It is desired to find a process which does not require a high dielectric constant etch stop/barrier layer.
U.S. Pat. No. 6,004,883 to Yu et al shows a dual damascene method without an etch stop layer. U.S. Pat. No. 6,083,822 to Lee shows a dual damascene method using a thin silicon nitride etch stop layer. U.S. Pat. No. 6,025,259 to Yu et al discloses a dual damascene method with etch stop layers. U.S. Pat. No. 6,071,809 to Zhao shows a method using an etch stop layer. U.S. Pat. No. 5,635,423 to Huang et al teaches various methods of forming a dual damascene opening. An etch stop layer such as silicon nitride or polysilicon is used. U.S. Pat. Nos. 5,935,762 to Dai et al and 5,877,076 to Dai show a double mask self-aligned process using a silicon nitride etch stop layer. U.S. Pat. No. 5,741,626 to Jain et al discloses a dual damascene process using a tantalum nitride etch stop layer.
A principal object of the present invention is to provide an effective and very manufacturable method of metallization in the fabrication of integrated circuit devices.
Another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials.
Yet another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials without using a high dielectric constant etch stop material.
A further object of the invention is to provide a double layered low dielectric constant material dual damascene metallization process.
A still further object of the invention is to provide a double layered low dielectric constant material via first dual damascene metallization process.
Another object of the invention is to provide a double layered low dielectric constant material dual trench first damascene metallization process.
Yet another object of the invention is to provide a double layered low dielectric constant material self-aligned dual damascene metallization process.
In accordance with the objects of this invention a double layered low dielectric constant material dual damascene metallization process is achieved. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first organic dielectric layer is deposited overlying the insulating layer. A second inorganic dielectric layer is deposited overlying the first dielectric layer. In a first method, a via pattern is etched into the second dielectric layer. The via pattern is etched into the first dielectric layer using the patterned second dielectric layer as a mask. Thereafter, a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings. In a second method, a trench pattern is etched into the second dielectric layer. Thereafter, a via pattern is etched through the second inorganic dielectric layer and the first organic dielectric layer to complete dual damascene openings. In a third method, a via pattern is etched into the second dielectric layer. Then, simultaneously, the via pattern is etched into the first dielectric layer and a trench pattern is etched into the second inorganic dielectric layer to complete dual damascene openings in the fabrication of an integrated circuit device.